1. Field of the Invention
The present invention generally relates to test of semiconductor integrated circuit devices, and more particularly to a test method for testing synchronous DRAMs which operate at higher speed than the maximum frequency of a test equipment.
2. Description of the Related Arts
The present memory devices are faster than conventional standard DRAMs (Dynamic Random Access Memory) and SRAMs (Static DRAM). These high speed synchronous devices are furthermore expected to have even higher clock speeds in the future. The current synchronous DRAMs have internal circuits operating in synchronous with an external system clock and represent very high operating speed, for example 7 nano seconds (=143 MHZ) in case of 64M synchronous DRAM. Accordingly, test equipment for testing the high speed devices is required to be equally fast as well.
However, faster test equipment is very expensive and therefore leads to a high investment cost. Further, in some cases the progress of the test equipment does not follow the development of the synchronous devices and therefore is simply not available for purchase. Accordingly, it would be beneficial if the high speed synchronous devices could be tested by using the existing low speed test equipment. Thus, the investment cost could be reduced and newly developed devices could be brought to market more quickly.
The inadequacies of the lower speed test equipment in testing high speed synchronous DRAMs are described as follows:
First, the test equipment has a minimum rate which corresponds to the limit frequency of a clock signal which the test equipment can generate. The clock signal frequency of the test equipment has a close relation to the clock cycle time, t.sub.cc, of the synchronous DRAM. For instance, if a synchronous DRAM operates at a speed of 143 MHZ, this synchronous device requires a system clock of equal or faster than 143 MHZ. However, a test equipment apparatus having 62.5 MHZ of the minimum rate cannot supply a proper system clock to the synchronous device.
Second, the minimum clock cycle of the test equipment must be short as the tested device. The minimum clock cycle means how long is maintained data `1` or `0` level of the control signals such as RAS/(Row Address Strobe), CAS/(Column Address Strobe), WE/ (Writer Enable), and CS/ (Chip Select) which are provided for controlling the functions of the synchronous DRAM. For example, if a control signal is changed from data `0` to data `1` before the minimum clock cycle time, e.g., 5 ns passes, we cannot assure that the synchronous device recognizes the data `0` level of the control signal.